Deep Reinforcement Learning-Based Optimization for IC Layout Design Rule Verification

Abstract

Design rule checking (DRC) in integrated circuit layout verification has become increasingly complex and time-consuming with the advancement of semiconductor technology nodes. This paper presents a novel deep reinforcement learning (DRL) based approach for optimizing DRC verification processes. The proposed method incorporates a distributed reachability certificate (DRC) and uncertainty-aware safety critic to address model uncertainties in verification workflows. By leveraging synthetic training data and transfer learning techniques, our framework achieves robust performance across different technology nodes while significantly reducing training-time violations. The system architecture integrates multiple functional modules, including a layout processing engine, DRL inference module, and verification orchestrator, achieving a 9.6x speedup in runtime performance compared to traditional methods. Experimental results on production-scale designs demonstrate 99.8% verification accuracy while reducing memory consumption by 50% and power usage by 47%. The framework exhibits superior scaling properties, maintaining near-linear performance up to extremely large designs. Comprehensive evaluations across three distinct datasets validate the effectiveness of our approach in handling complex design rules and edge cases. The method demonstrates particular strength in adapting to new technology nodes through efficient transfer learning mechanisms, addressing a critical challenge in modern semiconductor design verification.